The CPU core module
talks to the display using an
8bit wide data bus and two low active strobe signals
which I call AS (address strobe) and DS (data strobe).
The CPU transmits data always in pairs, one address
byte (latched into the display with AS) and one data
byte (latched in with DS). The timing varies a little,
but it seems that the address byte is set up about 32us
before AS, the AS pulse is about 16us, the byte remains
stable for about 48us. Then the data byte is set up,
after about 32us comes the DS pulse which lasts for
about 32us. The byte remains stable for about 16us.
This could be called
a write cycle. All display data
and control commands are transmitted this way.
The addresses 0..39
(0x00..0x27) match the 40 display
positions, beginning in the upper left corner:
The display has a
256 character ROM, which is more or less
ASCII compatible, full table see here.
A character is written
on the display by writing the
character code to the address of the desired display position.
There is a second
address area from 64 to 103 (0x40..0x67)
that seems to be the character attribute memory.
The addresses also match the display positions (constant
offset 64). Writing a 1 here makes the character blink,
writing a 0 turns blinking off.
Control commands are
write cycles with address 0x70..0x7F
and a data byte (usual 0x00). I saw the following commands:
0x71 second init command (data byte was 0x02 here)
0x79 contrast +
0x7A contrast -
0x7B first init command
0x7D first clear command
0x7E second clear command
The 0x7B 0x71 sequence
happens only after RESET.
All character write sequences begin with the 0x75 command
and end with the 0x7C command. If the display has to
be cleared (e.g. mode switching), 0x7D 0x7E follows the 0x75.
After the 0x75 comes always 15ms pause.
After the 0x7D 0x7E pair comes 1.5ms pause.
In normal time display
mode, the two seconds digits are
refreshed every second, and every minute, the entire
display gets refreshed.
In time setting mode, the entire display gets refreshed